The ambition of PLASMIC is to address the bottleneck caused by electrical interconnects and develop on-chip optical interconnect solutions based on plasmonically-enhanced nanoscale emitters. Nanoscale photonic components are desirable for on-chip communications because of density, speed and because reducing the size of the cavity might reduce the lasing threshold. Conventional photonics are limited in scale by the diffraction-limit to dimensions of half of the wavelength of light in the material. This limit does not apply to plasmonics, an optical mode that exists at the interface between a metal and a dielectric. Thus, they have a great potential for applications where down-scaling and confinement are primordial. One of the barriers for applying plasmonics is the large losses associated with the metals. Thus in PLASMIC alternative plasmonic metals will be investigated based on their potential for tuning, VLSI compatibility, deposition methods and achieving lower optical losses in the near-IR. I will focus on highly doped semiconductors, metal nitrides, as well as multi-layers and compounds to form new plasmonic materials. Specifically, I will evaluate the use of the field-effect to achieve the semiconductor-metal transition to tune the plasma frequency. New pioneering device concepts for plasmonic-photonic emitters on a silicon platform integrated with passive silicon photonic waveguides will be developed. To implement the gain medium for the lasers, I will exploit a novel nanowire (NW) integration approach: Template-Assisted Epitaxy. The unique advantages make it possible to grow III-V NWs on any orientation of silicon and aligned to lithographic features. The devices will be based on a hybrid cavity formed between the NW and a Si waveguide with gratings to provide feedback. My team and I will explore dimensional scaling potential as well as the energy efficiency of plasmonic and photonic devices operating both in a lasing as well as in a subthreshold operation mode.

Nowadays, microelectronics set the pace for the whole knowledge-based economy and society in terms of the ever rising demand for mobile devices and the exponentially growing internet data transfer. However, the widening gap between the increasing number of transistors on a single Si chip and the delivered performance indicates the approaching limits of classical device scaling. Additionally, this miniaturization results in severe energy dissipation in the interconnection of devices. A smart way to overcome this emerging power consumption crisis is to avoid heating by replacing the on-chip and/or chip-to-chip electrical interconnects with optical interconnects. Due to their direct bandgap, III-V compounds are ideal for the integration of photonics with Si-based electronics on the very same chip. This would enable large-scale optoelectronics integration hindered so far by coupling- and overlay issues introduced by state-of-the-art III-V bonding on Silicon. MODES will develop and investigate a novel approach for self-aligned monolithic integration of active and passive III-V optoelectronic devices on a Silicon platform. It focuses on the optimization of GaAs- and InP-based III-V growth within customized oxide templates. Moreover, this research aims at designing and fabricating doped, defect-free III-V heterostructures for electrically-driven optoelectronic devices integrated on Si. Owing to his experience in epitaxy as well as fabrication and characterization of group IV photonics, i.e. laser devices, the fellow complements ideally the competences of the group in III-V epitaxy and fabrication as well as knowledge of design and characterization of optoelectronic devices. Three objectives will be pursued: 1) Growth and integration of III-V material with Si-on-insulator waveguides 2) Design and fabrication of passive and active photonic devices based on integrated III-V materials and Si waveguides 3) Optical and electrical characterization of the photonic components.

Having developed a liquid scanning probe - microfluidic probe (MFP) - for creating spatially-defined microscale biochemical environments and microscale molecular assays within the ERC-BioProbe project, in this proof-of-concept project, - CellProbe - we seek to leverage this technology toward realization of a commercially viable single-cell analysis platform

We are entering the third era of computing: cognitive computing, which holds great promise in terms of deriving intelligence/knowledge from huge volumes of data. Today’s cognitive computers are based on the von Neumann architecture, in which the computing and the memory units are separated. Cognitive computing, however, is inherently data-centric, meaning that huge amounts of data need to be shuttled back and forth at high speeds, a task at which that architecture is highly inefficient. It is becoming increasingly clear that to build efficient cognitive computers, we need to transition to non-von Neumann architectures where memory and logic coexist in some form. Brain-inspired neuromorphic computing and the fascinating new area of memcomputing are two key non-von Neumann approaches being researched. The critical element in these novel computing paradigms is a very-high-density, low power, variable-state, programmable and non-volatile nanoscale memory device. A technological breakthrough that will lead us to this device will be a game-changer for cognitive computing. The goal of this project is to explore one such device concept that I co-invented at IBM Research - Zurich and which we have dubbed “projected memristor” or “projestor” for short. The projestor is indeed a memristor, i.e., a resistive element that remembers the history of the current that previously flowed through the device. The distinguishing feature of a projestor is that the physical mechanism of resistance storage is decoupled from the information retrieval process. In the first part of the project, we will design and fabricate projestor devices to establish the concept of projection and assess its merits and drawbacks. In the second part, we will expand the concept substantially to explore highly innovative projestor devices. In the third part, we will explore various applications of projestors in neuromorphic computing and memcomputing, with a particular focus on real-time data analytics.

The quantum information revolution aims at transforming information technology by engineering quantum systems, i.e. qubits, that can be used for quantum information processing (QIP), which allows to perform computations inaccessible to classical computers. In the quest for such systems, solid-state qubits alongside trapped ions currently are the leading candidates. One of the most advanced solid-state technologies to date is based on superconducting quantum circuits (SQCs), which makes use of Josephson tunnel junctions and their macroscopic quantum coherence between two superconducting islands. Due to recent advances in semiconductor-superconductor hybrid (SSH) devices, novel SSH-based qubit architectures have emerged, demonstrating improved properties compared to conventional SQCs, such as in-situ tunability while not being susceptible to flux noise. These novel SSH qubits make use of the true microscopic particle transport within SSH weak links. The main goal of the project is to unambiguously demonstrate SSH-based qubits as a viable and scalable platform for QIP by combining novel SQCs with advanced silicon-technology. The fellow will develop and characterise SSH weak links solely based on silicon (Si), which have the advantage of being fully CMOS compatible and consisting entirely of crystalline materials. Finally, these Si-based weak links will be implemented in novel SQCs, which will combine the good controllability of SQCs with the unique material quality of Si. This will allow the study of the underlying charge dynamics, giving insight into sources of loss, and offer new possibilities for complex architectures. The successful completion of this project will be a decisive landmark towards understanding and integrating such devices in larger circuits, which will be crucial a step towards a vital roadmap for their application in QIP.