Le but du projet MEMOIRE est de développer de nouvelles mémoires à grille flottante à nanocristaux en Si ou Ge visant à remplacer les mémoires flash actuelles. Cette nouvelle technologie, qui a acquis une grande maturité ces dernières années, se confronte aujourd’hui encore à des problèmes de reproductibilité, de compréhension des mécanismes de stockage des charges et de développement des composants, qui doivent être résolus avant son introduction dans l’industrie. MEMOIRE est un projet interdisciplinaire alliant l’engineering des composants à la physique pure, dans lequel les principes physiques fondamentaux sont utilisés pour lever des verrous technologiques à la frontière des applications. Ce projet permet de créer une chaîne complète de compétences de la manipulation / élaboration des NC, à la modélisation, fabrication et caractérisation électrique des transistors et des mémoires. Le principal challenge du projet est d’obtenir le contrôle parfait des structures élémentaires fabriquées afin de permettre la compréhension des mécanismes électriques locaux et la modélisation appropriée des composants. Le travail sera réparti en quatre tâches : 1) fabrication de la grille flottante à NC et des composants; 2) modélisation de la nanostructuration du substrat et auto-assemblage des NC ; 3) modélisation des dispositifs ; 4) fabrication et caractérisation électrique des dispositifs élémentaires. Grâce à la complémentarité des partenaires, le projet permettra des avancées majeures tant dans la compréhension des mécanismes de base que dans le développement de nouvelles architectures de composants. Le consortium s’attachera aussi particulièrement au transfert technologique des procédés mis en oeuvre en laboratoire vers le partenaire industriel.

The collaborative research project with enterprise (PRCE) IODA proposes to contribute to fundamental prospects in physics and microelectronics by developing a methodology for performing transmission electron microscopy (TEM) studies on working nanodevices. The consortium is composed of two partners: the CEMES-CNRS laboratory (Toulouse) and STMicroelectronics (Crolles). Combining the expertise of STMicroelectronics to select, characterize and prepare devices from their production lines with the expertise of CEMES for in situ TEM studies, we aim to develop original TEM in operando experiments on real devices. The originality of our approach is to observe and analyze physical quantities and processes in building blocks from the industry (transistor, flash memory, phase change memory) using TEM when they are submitted to an external stimulus (voltage and current). The project will be mainly focused on the quantitative mapping of the electric field and the electric charge distribution in devices at the nanoscale by electron holography (EH). The results will bring information on the local dielectric permittivity and capacitance for transistors and flash memories, the local electric resistivity and the thermal transition for phase change memories but also on the failure mechanisms of all these devices. These measurements by EH will be correlated to complementary TEM methods (conventional , high-resolution and electron spectroscopy) as well as electrical measurement performed of wafers before device extraction for a full understanding of structural, chemical and electrical properties at the nanometer scale. The project is thus divided into 3 main tasks: • Task 1 concerns the selection of devices of interest in the STMicroelectronics production lines by a local and full electrical characterization at the wafer level. Electrical based techniques will be performed on twin samples using nanoprobing and near field microscopy based techniques. • Task 2 aims at extracting and preparing the selected devices for in operando TEM experiments. The consortium will develop an advanced dedicated plateform for state-of-the-art TEM sample preparation with all modern equipment for sample extraction and thinning. The devices will be prepared before being electrically bonded to apply current/voltage on a dedicated TEM sample holder. Electrical control steps will be integrated in the preparation procedure to ensure the reliability of the TEM samples. • Task 3 is dedicated to in operando TEM experiments and to data analysis. After studying the local electric properties (electric field lines, potential and elementary charge distribution) by EH, additional structural and chemical TEM studies will be performed on the very same area of the device. The in operando experiments will be developed and performed at CEMES using a holography-dedicated electron microscope for in situ studies. The procedures and methodologies will then be transferred to STMicroelectronics. In addition, numerical simulations by finite element modeling will be carried out to take into account the two-dimensional projection of a three-dimensional field and the effects of the sample preparation. The IODA project will benefit from a highly favorable scientific environment, particularly with the access to a unique Hitachi HF3300C electron microscope (dedicated to holography experiments) installed in the context of a nationally funded EQUIPEX project “MIMETIS”. We thus aim to develop in operando TEM experiments for understanding and mastering of the physical phenomena and interactions as well as failure mechanisms in nanodevices at the nanoscale. Results will bring crucial information to STMicroelectronics for the development and optimization of (future) devices in terms of reliability, speed and power consumption. The developed methodology may also find application for the study of other type of devices. This project is therefore bridging a gap between industry and fundamental physics.

The 60GHz band has been explored for high data rate wireless communications in the last decade and the standard IEEE-802.15.3c was created in order to normalize this band for High data rate short range communications. At the end of the last decade, we have seen specific consortiums such as WiHD driven by SiBeam and WiGig driven by Intel created in order to define specific use cases and to prepare this new generation of High Data Rate wireless communication era. WiHD was mainly focused on the video streaming applications and didn’t give enough freedom for other use cases. Even if it is, the only one which already has offers yet commercial products for High definition Definition video uncompressed HDMI cable replacement, it seems that it would not win at the end of the day, due to the limitation described above. WiGig was created to cover video streaming and high data rate file transfer, for plugged and hand held devices. In the same time, the consortium has made an alliance with WiFi Alliance in order to integrate the 60GHz communication in the WiFi ecosystem, which clearly gives to this standard a big advantage over the others. The first generation of hand held WiGig chipset will be considered as a standalone add- on into the phone and will not share any function with the WiFi chipset , this generation is under Research and Development in the industry, in order to meet the market introduction time forecasted within the three next years. However, Iit will not meet the lowest power consumption and the programmability required for future applications. The next generation of chipset must be thought as a fully integrated function in the WiFi ecosystem, which means that the MAC, the Digital BaseBand (DBB), and the Radio Frequency Front-End (RFFE) will share the WiFi and WiGig bands and modulation schemes within same circuits, with high programmability behavior, even if this would not be a SOC, this generation has to be invented and would be on the market in range of 5 to 7 years. What we propose to make in this project is to prepare the second generation which will introduce, inside a unique programmable RFFE, innovative architectures for handling both the WiFi and WiGig standards, prepare for future evolution of these standards and enable interesting use cases. In summary, this project aims at reducing the global power consumption through an innovative interface approach, combining digital and analog processing in an optimal way. Furthermore, reuse of the architecture and circuits for both the 60GHz and the 2.5 / 5 GHz bands is emphasized to minimize the bill of materials. In order to build such devices and to take some “advantage” from the Moore’s law, we have propose to investigate a new “digital”digital- like IF-RF signal processing stage which will deliver/receive directly the 2.5GHz - 5GHz WiFi signal to/from the PA/LNA and which will be the IF signal generator/receiver for the 60GHz WiGig signal. This signal processor will integrate a 2.5GHz to 60GHz programmable frequency generator/synthesizer, which will deliver the right frequency for the right standard. All of these blocks will be highly re-configurable, and finally, in order to facilitate the test, we will introduce mmW mixer stage in order to deliver 60GHz signal, when WiGig standard will be selected on the chip.

Mid-infrared free-space absorption spectrometers have demonstrated label-free and real-time detection of multiple chemical and biological substances with an outstanding precision and versatility. However, they are bulky and high-cost, precluding their use in widespread high-volume applications. The MIR-Spec project will address these limitations by developing innovative silicon on-chip mid-infrared absorption spectroscopy sensors. The ground-breaking concept is to use subwavelength silicon nano-structures to develop a novel platform that leverages the wide transparency (up to ~8 µm wavelength) and large-volume fabrication processes of silicon, leading to significant breakthroughs in sensing applications. The MIR-Spec project is a “Projets de recherche collaborative - entreprises (PRCE)”, which gathers an academic research group (C2N), a Si foundry (STMircroelectronics) and an end-user (MirSense).