The eProcessor ecosystem combines open source software (SW)/hardware (HW) to deliver the first completely open source European full stack ecosystem based on a new RISC-V CPU coupled to multiple diverse accelerators that target traditional HPC and extend into mixed precision workloads for High Performance Data Analytics (HPDA), (AI, ML, DL and Bioinformatics). eProcessor will be extendable (open source), energy-efficient (low power), extreme-scale (high performance), suitable for uses in HPC and embedded applications, and extensible (easy to add on-chip and/or off-chip components), hence, the “e” used as a wildcard in eProcessor proposal name. eProcessor combines cutting edge research utilizing SW/HW co-design to achieve sustained processor and system performance for (sparse and mixed-precision) HPC and HPDA workloads by combining a high performance low power (architecture and circuit techniques) out-of-order processor core with novel, adaptive on-chip memory structures and management, as well as fault tolerance features. These software-hardware co-design solutions span the full stack from applications to runtimes, tools, OS, and the CPU and accelerators. eProcessor is able to pursue a full stack (SW and HW) research project by leveraging and extending the work done in multiple European projects like: European Processor Initiative, Low-Energy Toolset for Heterogeneous Computing, MareNostrum Experimental Exascale Platform, POP2 CoE, Tulipp, EuroEXA, and ExaNeSt. By doing so, we can improve the Technical Readiness Level and work with industrial partners that provide a direct path to commercialization. This can only be done with a combination of SW simulation, HW emulation using FPGAs, and a real ASIC prototype that demonstrates the full stack feasibility of the hardware and software. Finally, while the applications we use span IoT to HPC, the ASIC implementation will be in a technology node that can easily be adopted for a near-future HPC implementation.

CLEVER proposes a series of innovations in the area of hardware accelerators, design stack, and middleware software that revolutionize the ability of edge computing platforms to operate federatedly, leveraging sparse resources that are coordinated to create a powerful swarm of resources. CLEVER technologies will support the deep edge computing paradigm, moving computing services closer to the end user or the source of the data to reduce power consumption, reduce capacity requirements, and latency for mission critical applications. Furthermore, CLEVER will overcome traditional limitations of edge computing in terms of limited resource availability by providing an effective framework for seamless use of federated resources in the edge-cloud continuum. CLEVER will demonstrate processing solutions for AI at the edge through four use cases: (1) digital twin for in-factory optimization, (2) smart agriculture for high yield eco-farms, (3) fully automated material deployment, and (4) augmented reality for shopping sites. Through the achievement of its goals, the CLEVER project will help to position Europe at the forefront of the intelligent edge computing field, enabling growth across many sectors (manufacturing, agriculture, smart environments, augmented reality, and others). By lowering the barriers for utilising edge computing for artificial intelligence applications, CLEVER will open the door for European Industries and SMEs to leverage state of the art technologies, driving their development and growth as leaders in their sectors.

Electrification and autonomy drive the rapid evolution of modern vehicles, requiring increasing computational capabilities, coupled with safety and efficiency. The classical, decentralized multi- Electronic Control Units (ECU) architecture has significant drawbacks when it comes to scalability, and it is becoming untenable. The dominant megatrend pushes for an increasing number of key functionalities to be software-defined, with the direct implication that the software content (lines-of-code) in a vehicle will grow by 10x in just 5 years, to 1 billion by 2030. From a hardware viewpoint, increased complexity and autonomy requires a more centralized approach to on-board computing to curtail cost, latency and bandwidth bottlenecks of the in-vehicle network. Centralizing the E/E architecture requires merging multiple Electronic Control Units (ECUs) into powerful, fully programmable Domain Control Units (DCUs) or Zonal Control Units (ZCUs). To address this paradigm shift, the Rigoletto project will establish the foundation for a next-generation Automotive Hardware Platform based on the open RISC-V instruction set architecture (ISA), bolstering and securing Europe's leading role in the automotive electronics industry. The project aligns with the high-level goal of EU Chips Joint Undertaking and the of the industry-led Vehicle of the Future initiative: namely, the creation of a RISC-V based automotive hardware platform strongly linked with the formation of an open, software-defined vehicle ecosystem led by European automotive manufacturers and suppliers. Rigoletto aims at developing RISC-V intellectual property (IP) components, including processor cores, accelerators, interconnects, memory hierarchy and peripheral subsystems. A wide range of performance profiles will be targeted for next-generation DCUs and ZCUs, to enable increasingly electrified, automated, and connected vehicles.